1. Field
This disclosure relates to generating a clock signal.
2. Background Information
Integrated circuits (ICs), such as processors or microprocessors, for example, typically employ circuitry for providing a clock signal to elements of a circuit embodied on such an IC. Clocking, that is applying a clock signal to an IC, is well-known and, at least in part, allows the elements of an IC, such as a processor, for example, to operate synchronously or nearly synchronously. One common technique for providing such a clock signal, or clocking, an integrated circuit is to employ a clock circuit, such as, for example, a phase locked loop (PLL), a delay locked loop (DLL), or a frequency locked loop (FLL). Of course, other techniques for providing a clock signal exist. Such clock circuits are well-known to those of skill in the art and are typically configured as a feedback loop which may allow the clock signal being generated to be compared with a reference clock signal and adjusted until the two signals are xe2x80x9cphase lockedxe2x80x9d or substantially in phase. Techniques for comparing these signals and locking such a clock circuit vary and may depend on the particular embodiment. Typically, a clock circuit embodied in an IC, such as a processor, for example, clocks the IC at some frequency multiple of an external electronic signal. This signal is often referred to as a system clock or bus clock and may be generated, for example, by well-known oscillator circuits, which may include a ceramic or crystal oscillator. As clock frequencies increase in ICs, generating such clock signals based on such an external reference signal may become problematic due, for example, to clock jitter. Clock jitter, at a high level, may be defined as phase variation in such a clock signal from one phase to another of such a signal. Therefore, alternative methods of generating a clock signal for an IC may be desirable.